1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to a semiconductor device including double diffused metal oxide semiconductor (hereinafter referred to as “DMOS”) transistors.
2. Description of the Background Art
As an example of a semiconductor device for switching a heavy current, a semiconductor device including DMOS transistors is described. As shown in FIG. 30, an N− epitaxial layer 102 is formed on a p− silicon substrate 101. An N+ buried diffusion region 103 is formed between a p− silicon substrate 101 and an N− epitaxial layer 102. In addition, a P+ buried diffusion region 104 is formed between the N+ buried diffusion region 103 and the N− epitaxial layer 102.
An N diffusion region 107 is formed on the surface of the N− epitaxial layer 102. A P diffusion region 106 is formed so as to surround this N diffusion region 107 around the periphery. In addition, a P diffusion region 105 which contacts the P diffusion region 106 and which reaches the P+ buried diffusion region 104 is formed on the surface of the N− epitaxial layer 102. A gate electrode 110 is formed above the surface of the P diffusion region 106, which is located between the N diffusion region 107 and the N− epitaxial layer 102, with an insulating film interposed in between.
A source electrode 111 which is electrically connected to the N diffusion region 107 is formed. In addition, a silicon oxide film 109 for isolation is formed on the surface of the N− epitaxial layer 102. A drain electrode 112 is formed on the side opposite to the source electrode 111, with a silicon oxygen film 109 located in between. The drain electrode 112 is electrically connected to the N diffusion region 108, which is formed in the N− epitaxial layer 102. A semiconductor device according to a prior art is configured as described above.
Though, in a conventional semiconductor device, the electric field tends to be concentrated on the corner parts of the P diffusion region 106, as shown in FIG. 31 the electric field which is concentrated on the corner parts is relaxed by a depletion layer which extends from the P+ buried diffusion region 104 (RESURF effect) in the above described semiconductor device.
Thereby, in this semiconductor device, the withstanding voltage can be increased to the level based on the width L of the depletion layer wherein the depletion layer edge which extends towards the side of the N diffusion region 108 and the depletion layer edge which extends towards the side of the P+ buried diffusion region 104 from the interface between the N− epitaxial layer 102 and the P+ buried diffusion region 104 are in the greatest proximity to each other.
On the contrary, however, the withstanding voltage is limited by this part where both depletion layer edges are in the greatest proximity to each other in this semiconductor device. In order to further increase the withstanding voltage it is necessary to make the distance between both depletion layer edges longer and to achieve this objective measures for increasing the film thickness of the N− epitaxial layer 102 are effective.
In the case that the film thickness of the N− epitaxial layer 102 is made thicker, however, it is necessary to form the P diffusion region 105, or the like, for isolating the N− epitaxial layer 102 correspondingly deeper. In addition, in the case that a vertical type NPN transistor, or the like, is formed as a semiconductor element, a current flows in the vertical direction and a problem arises that the resistance of the semiconductor device increases in this case.